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[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[assembly language] saa7111_2

Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A/D chip to control the collection, image data are stored in synchronous FIFO- AL422B
Platform: | Size: 1024 | Author: 古韦剑 | Hits:

[VHDL-FPGA-Verilog] sdh

Description: 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform
Platform: | Size: 6144 | Author: liu | Hits:

[VHDL-FPGA-Verilog] simple_fifo

Description: verilog HDL原码 一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
Platform: | Size: 1024 | Author: zxz | Hits:

[File Format] documentsoffifo

Description: 介绍FIFO的文章，关于同步FIFO或者异步FIFO-FIFO introduced an article on synchronous or asynchronous FIFO FIFO
Platform: | Size: 545792 | Author: 草草 | Hits:

[JSP/Java] cache4j_0.4_src

Description: cache4j是一个有简单API与实现快速的Java对象缓存。它的特性包括：在内存中进行缓存，设计用于多线程环境，两种实现：同步与阻塞，多种缓存清除策略：LFU, LRU, FIFO，可使用强引用(strong reference)与软引用(soft reference)存储对象。-cache4j is a simple API and achieving rapid Java Object Cache. Its features include : in memory for caching, designed for multi-threaded environment, the two realized : synchronous and obstruction, cache removal strategies : LFU, LRU, FIFO, can be invoked to use strong (strong reference) with the use of soft (soft referenc e) Storage object.
Platform: | Size: 51200 | Author: ytr | Hits:

[VHDL-FPGA-Verilog] syn_fifo

Description: 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
Platform: | Size: 1024 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] FIFO_Buffer

Description: 同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序，erilog编写~具有较强的参考价值~ -Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~
Platform: | Size: 69632 | Author: 张勇奇 | Hits:

[VHDL-FPGA-Verilog] FIFO_Syn

Description:
Platform: | Size: 25600 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Platform: | Size: 2048 | Author: 彭帅 | Hits:

[SCM] fifo

Description: 一个同步FIFO，包括testbench，-A synchronous FIFO, including the testbench,
Platform: | Size: 1024 | Author: 张丰 | Hits:

[Multimedia program] sfifo

Description: 此文件为同步FIFO的实现源码，同步FIFO可用于硬件中两种总线或器件的缓冲，以保证功能的实现。-This document is the realization of source synchronous FIFO, Synchronous FIFO can be used for two types of hardware or device bus buffer to ensure the realization of function.
Platform: | Size: 2048 | Author: 小明 | Hits:

[Other] fifo

Description: 同步fifo的原代码,给出了经典的同步fifo原代码，希望对大家有所帮助-synchronous fifo code
Platform: | Size: 2048 | Author: 画生 | Hits:

[Software Engineering] fifo

Description: 异步fifo的经典讲解，包括亚稳态的产生，同步电路的构造，fifo电路的结构，源代码实现。-Asynchronous fifo on the classic, including the emergence of metastable, the structure of synchronous circuits, fifo circuit structure, the source code to achieve.
Platform: | Size: 3224576 | Author: 王玉 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 同步和异步FIFO，VHDL实现。希望对大家有所帮助。-Synchronous and asynchronous FIFO, VHDL implementation. We want to help.
Platform: | Size: 589824 | Author: Jun | Hits:

[VHDL-FPGA-Verilog] fifo-VerilogHDL

Description: 利用VerilogHDL语言编写的同步FIFO，异步FIFO的编写及其注释-VerilogHDL language using synchronous FIFO, asynchronous FIFO, write and comment
Platform: | Size: 5120 | Author: 王体奎 | Hits:

[VHDL-FPGA-Verilog] Synchronous FIFO

Description: 用16*8 RAM实现一个同步先进先出（FIFO）队列设计。由写使能端控制该数据流的写入FIFO，并由读使能控制FIFO中数据的读出。写入和读出的操作由时钟的上升沿触发。当FIFO的数据满和空的时候分别设置相应的高电平加以指示(mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writing enable terminals and controls read of data in the FIFO by the read enable. The operation of writing and reading is triggered by the rising edge of the clock. When the data of FIFO is full and empty, set the corresponding high level to indicate)
Platform: | Size: 264192 | Author: 渔火 | Hits:

[Other] 同步FIFO设计

Description: First Input First Output的缩写，先入先出队列，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。(Classic synchronous FIFO design)
Platform: | Size: 268288 | Author: 见到过的都是 | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
Platform: | Size: 2048 | Author: 大黄黄黄 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo模块，改模块使用同步fifo设计，里面包含一些设计技巧，读延迟最少(The module of FIFO is modified by using synchronous FIFO, which contains some design skills and the least latency.)
Platform: | Size: 3072 | Author: 林林明 | Hits:
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